Synopsys Proteus™ full-chip mask synthesis smart manufacturing solutions enabling technologies down to 3nm and below. With the Synopsys Proteus family you can achieve exceptional precision, efficiency and speed in proximity correction, model building for correction, and analyzing proximity effects on corrected and uncorrected IC layout patterns, revolutionizing your chip fabrication process. The Synopsys Proteus full-chip mask synthesis family are the products of choice for leading edge IDMs and foundries and have been production proven for two decades with support for the latest EUV lithography processes. Synopsys Proteus 2023.12 Linux64 Tested Picture Key Benefits Largest Lithography Entitlement Industries first and most deployed inverse lithography solution with native curvilinear design and mask support. Fast Turn Around Time AI driven solutions with advanced...
Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, delivers the highest levels of design efficiency for capacity and performance. It leverages a common data-model to integrate design, die-to-die routing, native system analysis, verification, and signoff in a single environment. Synopsys 3DSO.ai, industry’s first autonomous AI optimization solution for 2.5D and 3D heterogeneous design and integration, seamlessly integrates with 3DIC Compiler to maximize system performance and quality of results at a rapid pace for thermal integrity, signal integrity, and power network design. Ensuring system technology co-optimization (STCO), Synopsys 3DIC Compiler is certified by all foundries and leveraged successfully by customers in dozens of designs. Key Benefits Unmatched Scalability System-of-chips integration over hundreds of billions of transistors High Productivity Fast exploration and design...
Synopsys RTL Architect product represents the industry’s first physically-aware RTL analysis, exploration, and optimization system with signoff technology integration. Synopsys RTL Architect uses a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. Built on a unified data model, Synopsys RTL Architect directly leverages Synopsys world-class implementation and golden signoff solutions, including Synopsys PrimePower RTL, to deliver results that are accurate early in the design cycle. Synopsys RTL Architect enables designers to significantly reduce RTL development time and to achieve “Simply Better RTL.” Key Benefits Increase Productivity Reduce project schedule with faster runtimes and fewer frontend – backend iterations Predict PPA Fast, implementation prediction engine ensures the...
Raphae FX is the gold standard, 2D and 3D resistance, capacitance and inductance extraction tool for optimizing on-chip parasitic for multi-level interconnect structures in small cells. As a reference field solver, Raphael FX provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael FX are included as part of their design reference guides. Synopsys Raphael FX 2024.03 Linux64 Tested Picture Benefits Analyze complex on-chip interconnect structures and the influence of process variation Create a parasitic database for both foundries and designers to study the effect of design rule change Generate accurate capacitance rules for layout parameter extraction tools Interface with Sentaurus Structure Editor to create and analyze arbitrary and complex 3D shapes...
