IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins. HDL Works IO Checker 5.2 Rev1 Win/Linux Tested Picture The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour. Once the project and its rules are...
HDL Companion is the HDL designer’s Swiss army knife. It will help you to get and keep a good overview of any HDL design, including third party IP, legacy code and other HDL sources. Complete design directories and design files are dragged into HDL Companion and a complete design overview is created in seconds, uncovering information regarding numerous aspects of the design. The GUI offers many ways to navigate through the design and explore the details you’re looking for. HDL Works HDL Companion 3.3 Rev3 Win/Linux Tested Picture The embedded fuzzy parsers accept any SystemVerilog, VHDL or mixed HDL design code; even if the code is incomplete or contains errors. Syntactically correct HDL can also be linted to find problems...
EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you’re creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language – VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project. HDL Works EASE 9.5 Rev7 Win/Linux Tested Picture Features & Benefits Graphical design environment with automated generation of hierarchical VHDL or Verilog code Standards compliant: – VHDL: IEEE-1076 87, 93 & 2008 – Verilog: IEEE-1364 95, 2001,...
The first release of Sigasi® Visual HDL™ (SVH™) for 2025 features various UX improvements, a new VHDL linting rule and improved VHDL highlighting, and many small fixes. SVH 2025.1 adds many UX improvements and gives some extra love to VHDL. We are expanding the set of Code Lenses. They allow to open the State Machines Diagram, add unmapped files to the project, export documentation, and one to export the compilation order. Additionally, Code Lenses can now individually be enabled and disabled. We are also introducing a variant of Code Lenses, Inlay Hints. These fulfill the same action as Code Lenses—providing extra contextual actions or information—but they are displayed inline rather than on a line above the code. Exploring your design or testbench top-down has never been as...
Sigasi Visual HDL (SVH) is an HDL platform for VHDL and SystemVerilog that gives hardware designers and verification engineers better insight during the design process. SVH enables users to easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. It does so by standardizing the concept of an HDL design project, shifting simulation and synthesis projects into a world of integrated development, synchronous visualization, and shift-left validation. Sigasi Visual HDL Enterprise Edition 2024.1 Tested Picture SVH enables hardware designers and verification engineers to easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. It does so by standardizing the concept of an HDL design...
