PathWave RFIC Design (GoldenGate) 2024 includes new capabilities which includes new Fast Envelope algorithm, Krylov GPU acceleration, SystemVue VTB updated package, updated support for TMI, new circuit simulation models, improvements in Vrituoso Integration and usability improvements.
Go beyond traditional RF simulation to design, analyze, and verify radio frequency integrated circuits (RFICs). Achieve confidence with steady-state and nonlinear solvers for design and verification. Wireless standard libraries accelerate the validation of complex RFICs.
- accurately model components on silicon chips
- optimize designs with sweeps and load-pull analysis
- simulate RF designs in the Cadence Virtuoso and Synopsys Custom Compiler environments
- increase performance using Monte Carlo and yield analysis
- assess EVM for the latest communication standards early in the design phase
- utilize the latest foundry technology immediately
