IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins.
HDL Works IO Checker 5.2 Rev1 Win/Linux Tested Picture
The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour.
Once the project and its rules are defined it is a simple task to keep the FPGA and PCB data consistent. All out-of-date files are processed in one action and all changes are reported.
Features & Benefits
- Compare FPGA and PCB pin names using regular expressions
- Create & update FPGA constraint file
- Automatic rule generation
- Voltage checks for power pins
- User directed acceptance of verified differences
- One click verification and consistency
- Reports incremental changes in pin- and net list
- Concentrate on a dozen differences instead of a thousand lines
- Fits in any design flow
- HTML report
