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Catapult has the broadest portfolio of hardware design solutions for C++ and SystemC-based High-Level Synthesis (HLS). Catapult’s physically-aware, multi-VT mode, with Low-Power estimation and optimization, plus a range of leading Verification solutions make Catapult HLS more than just “C to RTL”. Catapult High-Level Synthesis Solutions Catapult High-Level Synthesis solutions deliver C++ and SystemC language support, FPGA and ASIC independence, ASIC power estimation and optimization plus the latest in Physically aware multi-VT area and performance optimization to elevate your designs. C++/SystemC Synthesis A comprehensive HLS flow taking C++ or SystemC as the design input and optimally targeting ASIC, eFPGA or FPGA implementations tuned for frequency and target technology. Low-Power Solutions When it comes to early design space exploration, power estimation, and...

PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power estimation for both RTL and Gate-level designs, early power checks to quickly find power issues during RTL development and clock and memory gating to optimize the design for power. PowerPro Power Analysis & Optimization Platform PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power analysis for both RTL and gate-level designs, early power checks to quickly find power issues during RTL development and clock and memory gating to optimize the design for power. RTL Power Estimation PowerPro RTL Power Estimation delivers highly accurate estimations that are within 10% of signoff. This technology is built on advanced engines...

Tessent Silicon Lifecycle Management solutions include advanced debug, safety & security features and in-life data analytics to meet the evolving challenges of today’s silicon lifecycle. Ensure the highest test quality, accelerate yield ramp and improve safety, security and reliability across the silicon lifecycle using best-in-class solutions for design-for-test (DFT), debug and in-life monitoring plus powerful data analytics. Tessent Advanced DFT Address the challenges of in-system test for today’s complex SoCs and chiplets with market-leading logic and memory test products that combine capabilities in a powerful test flow to ensure total chip coverage. Tessent Embedded Analytics Close productivity gaps using actionable insights from embedded analytics that shorten total development time, accelerate debug and reduce risk and cost to ensure timely market...

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Top Features and Benefits High Performance Simulation Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations The industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems Support for the latest Verification Libraries, including Universal Verification Methodology (UVM) Support for VHDL verification libraries, including OSVVM and UVVM. Advanced Debugging Integrated multi-language debug environment enables automating time-consuming design analysis tasks and fixing bugs...

ALINT-PRO is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design. Single Framework...

Active-HDL is a Windows based, integrated FPGA design creation and simulation solution for team-based environments. Active-HDL’s integrated design environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs. The design flow manager evokes 200+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from AMD, Intel, Lattice, Microchip, Quicklogic and more. Top Features and Benefits Project Management Unified Team-based Design Management maintains uniformity across local or remote teams Configurable FPGA/EDA Flow Manager interfaces with 200+ vendors tools allows teams to remain on one...