EDA 第7页
Electrical & Power Engineering softwares.
Xtensa Xplorer serves as a cockpit for basic design management, invocation of Tensilica processor configuration tools (Xtensa processor generator, TIE Compiler) and software development tools. Xtensa Xplorer is particularly useful for the development of TIE (Tensilica Instruction Extension) instructions – designer-defined instruction extensions to the Xtensa processor – that maximize performance for a particular application. Different Xtensa processor and TIE configurations can be saved, profiled against the target C/C++ software, and compared. Xtensa Xplorer even includes automated graphing tools that create spreadsheet-style comparison charts of performance. Available versions: 10.1.11 , 9.0.18 , 8.0.8 , 7.0.9 ,… Xtensa Xplorer dramatically accelerates the processor optimization cycle by providing an automated, visual means of profiling and comparing different processor configurations. Since it only...
PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power estimation for both RTL and Gate-level designs, early power checks to quickly find power issues during RTL development and clock and memory gating to optimize the design for power. Available versions: 2024.2 , 2022.1 , … Siemens PowerPro 2024.2 Linux Tested Picture PowerPro Power Analysis & Optimization Platform PowerPro offers the most comprehensive set of features to RTL designers to “design-for-low-power”. It offers power analysis for both RTL and gate-level designs, early power checks to quickly find power issues during RTL development and clock and memory gating to optimize the design for power. RTL Power Estimation PowerPro RTL Power Estimation delivers highly accurate estimations...
PathWave Signal Generation is a signal creation for a wide range of general purpose or standards-based signals. Comprehensive PC-based software for flexible signal creation. Cellular, wireless connectivity, aerospace/defense, broadcasting and general purpose applications. Supports a wide variety of signal generation hardware. PathWave Signal Generation Desktop 2025 v7.0.0 Tested Picture Create Performance-Optimized Reference Signals Create calibrated signals, validated by Keysight, that conform to industry standards to help enhance the characterization and verification of your devices with or without impairments. Validate Component, Transmitter and Receiver Testing Easily create and playback customized waveforms for component testing with virtually distortion-free test signals. Generate fully channel-coded signals including real-time mode to evaluate the throughput of your receiver. Impairments can be also added to evaluate receiver...
Proteus ProGen models are empirical compact models reflecting the performance of a lithography process. Model parameters are determined by fitting experimental data. The Proteus Modeling Platform (PMP) provides a single environment for calibrating those parameters with a high degree of automation and tuning them for optimum performance in downstream applications. Synopsys ProGen 2023.12 Linux64 Tested Picture ProGen, Proteus’ highly customizable solution calibrates a single model that is utilized by both the space- and frequency-domain engines.
Synopsys Proteus™ full-chip mask synthesis smart manufacturing solutions enabling technologies down to 3nm and below. With the Synopsys Proteus family you can achieve exceptional precision, efficiency and speed in proximity correction, model building for correction, and analyzing proximity effects on corrected and uncorrected IC layout patterns, revolutionizing your chip fabrication process. The Synopsys Proteus full-chip mask synthesis family are the products of choice for leading edge IDMs and foundries and have been production proven for two decades with support for the latest EUV lithography processes. Synopsys Proteus 2023.12 Linux64 Tested Picture Key Benefits Largest Lithography Entitlement Industries first and most deployed inverse lithography solution with native curvilinear design and mask support. Fast Turn Around Time AI driven solutions with advanced...
Silvaco offers a full IC-CAD design flow including design capture, circuit simulation, layout design, physical verification, parasitic extraction and reduction, and post-layout analysis including statistical variation, and yield analysis. Silvaco SmartSpice Pro 2024 v5.9.2 Linux64 Tested Picture Schematic Editor Gateway is a highly productive environment with intuitive editing, capacity to support large and complex hierarchical or flat designs, ability to automatically generate symbols from existing legacy netlists and support for industry standard netlist and interface formats. It features tight integrations to Silvaco TCAD and analog custom design tools. Layout Editor Expert is a hierarchical IC layout editor featuring high capacity and flexible use across many silicon technologies in analog, mixed-signal, RF and digital circuits. As a key part of Silvaco’s custom IC...
Synopsys 3DIC Compiler, a unified exploration-to-signoff platform, delivers the highest levels of design efficiency for capacity and performance. It leverages a common data-model to integrate design, die-to-die routing, native system analysis, verification, and signoff in a single environment. Synopsys 3DSO.ai, industry’s first autonomous AI optimization solution for 2.5D and 3D heterogeneous design and integration, seamlessly integrates with 3DIC Compiler to maximize system performance and quality of results at a rapid pace for thermal integrity, signal integrity, and power network design. Ensuring system technology co-optimization (STCO), Synopsys 3DIC Compiler is certified by all foundries and leveraged successfully by customers in dozens of designs. Key Benefits Unmatched Scalability System-of-chips integration over hundreds of billions of transistors High Productivity Fast exploration and design...
Modelithics Qorvo GaN Library 24.5.4 for use with Keysight Technologies’ Advanced Design System (ADS) and Cadence AWR Design Environment®. This release is compatible with Keysight ADS 2022 – 2024 Update 2 and Cadence AWR Design Environment 16 and 17.3+. The Modelithics Qorvo GaN Library is backward compatible with previous Modelithics library releases. Available versions: 24.x , 21.x ,… Modelithics Qorvo GaN Library 21.4 Tested Picture This latest version offers new models for Qorvo’s QPD1035 (40 W) and QPD1035L (40 W) discrete GaN-onSiC HEMTs. The QPD1035 and QPD1035L are 40 W devices with load-pull validation of 4, 5 and 6 GHz and a max frequency of 6 GHz. Both models are non-linear models and include temperature scaling. Also available with this...
PathWave RFIC Design (GoldenGate) 2024 includes new capabilities which includes new Fast Envelope algorithm, Krylov GPU acceleration, SystemVue VTB updated package, updated support for TMI, new circuit simulation models, improvements in Vrituoso Integration and usability improvements. Go beyond traditional RF simulation to design, analyze, and verify radio frequency integrated circuits (RFICs). Achieve confidence with steady-state and nonlinear solvers for design and verification. Wireless standard libraries accelerate the validation of complex RFICs. accurately model components on silicon chips optimize designs with sweeps and load-pull analysis simulate RF designs in the Cadence Virtuoso and Synopsys Custom Compiler environments increase performance using Monte Carlo and yield analysis assess EVM for the latest communication standards early in the design phase utilize the latest foundry...
Arteris IP created the new technologies in FlexNoC 4 AI based on its learning from some of the world’s leading AI and DNN SoC design teams. Arteris IP customers developing AI chips include autonomous driving pioneer Mobileye, who recently licensed Arteris IP FlexNoC and Ncore interconnect IP for its next-generation EyeQ systems, Movidius, Cambricon, Intellifusion, Enflame, Iluvatar CoreX, Canaan Creative, and four other companies that have not been publicly announced. New capabilities in FlexNoC 4 and the new AI Package include: Automated topology generation for mesh, ring and torus networks – FlexNoC 4 AI enables SoC architects to not only generate AI topologies automatically but also edit generated topologies to optimize each individual network router, if desired. Multicast – FlexNoC 4 AI intelligent multicast optimizes the usage of on-chip and...
