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SIMetrix/SIMPLIS 是一款先进的仿真工具，专为高效设计电力电子电路而优化。SIMetrix/SIMPLIS 将精度和收敛性完美结合在一个独特而强大的设计环境中，使电源设计的仿真速度提升 10-50 倍。 可用版本: 9.x , 8.x ,… SIMetrix-SIMPLIS Elite with MDM 8.40 Tested Picture 波形查看器功能 固定探针的独立 X 轴 现在可以强制固定探针生成的曲线图具有独立的 X 轴，从而实现独立缩放。此前，只能在绘制曲线后手动设置 X 轴。 原理图编辑器功能 LTspice® 兼容性 原理图编辑器现在可以直接打开 LTspice® 原理图；只需像往常一样打开文件即可。如果所有使用的模型都受 SIMetrix 仿真器支持，则只需进行少量更改即可运行原理图仿真。 设计验证模块功能 测试计划编辑器 现在可以使用内置的测试计划编辑器创建和编辑测试计划。内置的测试计划编辑器不仅无需第三方电子表格或文本编辑器软件，还提供各种单元输入方面的帮助。这包括下拉选择列表和参数输入辅助。 除了单元格输入辅助外，测试计划编辑器还提供实时错误检查。将鼠标悬停在彩色单元格上即可获取更多信息。 测试计划向导 动态创建 DVM 测试计划，仅包含所需的目标和输入。 提供三个向导： 直流-直流 1 输入 1 输出 直流-直流 1 输入 2 输出 交流-直流 1 输入 1 输出 SIMPLIS 仿真器的新功能 变压器绕组损耗细分 使用 MDM 模拟变压器损耗时，“MDM 结果窗口”中的“变压器设计”选项卡现在提供每个绕组的详细损耗文本细分。用户现在可以查看每种类型（直流偏置、交流传导、趋肤效应和邻近效应）的绕组损耗在每个绕组中的具体数值。 MDM 数据库新增磁芯材料 MagDB 数据库新增 87 种软功率磁性材料。用户可以在 MagDB 窗口中查看这些材料的属性，也可以在 MDM 主窗口的“磁芯”选项卡中选择使用。 用户自定义磁芯损耗分析方程 在向 MDM 数据库添加新的磁芯材料或修改现有材料时，用户现在可以自定义磁芯损耗计算方程。具体操作方法是：打开 MagDB，从列表中选择一种磁芯材料，然后单击“分析方程”按钮，即可打开“磁芯损耗分析方程编辑器”。 该方程用于模拟正弦磁通激励引起的铁芯损耗，输出损耗单位为 W/m³，其输入参数包括频率（单位：Hz）、峰值磁通密度（单位：T）、温度（单位：°C）和直流偏置（单位：A/m）。用户可以使用 JavaScript 编写任意表达式，利用部分或全部输入参数来计算材料的体积铁芯损耗。一些铁芯材料制造商在其数据手册中提供了此类方程。 PFC POP 触发原理图 要启动 SIMPLIS 交流分析，必须先成功完成 SIMPLIS POP 分析。对于具有交流输入的 PFC 电路原理图，目前 POP 分析只能在非常特定的条件下才能成功，即开关频率为交流线路频率的整数倍——而许多 PFC 电路并非如此。 新型 PFC POP 触发器原理图设备可对模拟控制 PFC 整流电路的原理图进行 SIMPLIS POP 和交流分析，包括开关频率可变的电路以及开关频率并非交流线路频率整数倍的电路。 PFC POP 触发器可轻松切换交流和直流输入，并可与数字万用表 (DVM) 或电源配合使用，快速比较 PFC 在交流和直流输入下的波特图。 新增的测试功能可使 PFC POP 触发器与数字万用表 (DVM)...

Synplify FPGA综合软件是业界公认的高性能、高性价比FPGA设计标准。Synplify软件支持最新的VHDL和Verilog语言结构，包括SystemVerilog和VHDL-2008/2019。此外，该软件还支持来自众多FPGA厂商的FPGA架构，例如Achronix、Intel、Lattice、Microsemi和AMD/Xilinx，所有架构均可通过单一的RTL和约束源进行综合。 可用版本: 2025.x ,2024.x ,2023.x ,… Synopsys Synplify FPGA 2024.09 Win/Linux64 Tested Picture 此外，Synplify 综合工具提供高性能、更快的运行速度、面积优化以降低成本和功耗，以及增量式和团队设计功能，从而加快 FPGA 设计开发速度。 它包含 TMR 和 HAMMING-3 for FSM 等功能，可自动创建高可靠性设计，例如用于医疗、汽车、工业自动化、通信、军事和航空航天等领域的设计。 Synplify 功能 高级 Verilog、SystemVerilog 和 VHDL 支持 最佳结果质量 (QoR)，实现时序性能和面积/成本降低 支持高可靠性和安全关键型设计，包括 DO-254、ISO 26262 和 IEC 61508 标准 加速运行时间，运行时间最高可达 3 倍，每个许可证最多支持 8 个处理器 分布式综合，支持单机或多机应用 静态时序分析和报告，用于衡量设计性能，并进行反向注释，以关联布局布线后的性能。 集成 Identify RTL 调试器，可快速查找功能错误 故障注入和调试支持，用于衡量安全性和高可靠性特性的有效性 HDL Analyst 交互式图形分析和调试工具用于设计诊断、问题隔离以及功能和性能分析 通过 HDL Analyst 和分层调试流程进行高级设计调试和诊断 FSM Compiler 和 FSM Explorer 用于从 RTL 中自动提取和优化有限状态机 与 VCS® 和 Verdi 集成 支持脚本和 Tcl/Find，用于流程自动化以及可自定义的综合、调试和报告 More Information in English: Synopsys Synplify FPGA 2025.03 SP1 Win/Linux64

ImSym – Imaging System Simulator, a groundbreaking virtual prototyping platform for imaging systems, encompassing lenses, sensors, and image signal processors (ISPs). By integrating components of the imaging chain into a comprehensive end-to-end simulation platform, ImSym enables tailored optimizations of any imaging system, facilitates team collaboration, and dramatically reduces the risks of issues in later development stages. With accuracy powered by industry-proven CODE V® and LightTools® optical design software and a quantitative end-to-end simulation flow, ImSym reduces the need for physical prototypes and delivers simulations that can directly translate into production-ready designs. Synopsys ImSym 2024.09 Tested Picture Enhance Your Optical System Development with ImSym Visualize images with precise, quantitative data Streamline your development process Deliver your next great imaging product to...

StarVision® PRO represents the state-of-the-art in debug solutions for advanced electronic SoCs. The incorporation of Concept’s leading visualization and detection technology enables rapid cause-effect analysis for efficient functional analysis. This advanced and unique mixed-mode debug platform seamlessly combines SPICE and transistor analysis from our market leading SpiceVision PRO tool with digital RTL and gates from our advanced RTLvision PRO tool. It is fully customizable and incorporates many advanced features not available in other debug solutions, to handle the most complex of SoC platforms. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair StarVision PRO 2025.0 Win Tested Picture StarVision PRO 2025 is a major release, the following features were fixed and/or added: Show the logic value...

GateVision® PRO is the third generation of graphical, gate-level netlist analyzers and viewers from Concept Engineering. Completely rewritten to run on modern 64bit platforms to handle the largest designs and SoCs, GateVision PRO provides a range of powerful debug and comprehension capabilities. These include intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair GateVision PRO 2025 Win Tested Picture GateVision PRO 2025 is a major release, the following features were fixed and/or added: Show the logic value at the mouse position in the tooltip of the Wave window. Speed-up displaying the members of large vectors in the Wave window. Add...

SpiceVision PRO takes SPICE netlists and models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, debug, and optimization at the transistor-level. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair SpiceVision PRO 2025.0 Win Tested Picture SpiceVision PRO 2025, the following features were fixed and/or added: Add new GUI API commands gui tab showPlusMenu and gui tab hidePlusMenu to control the display of the “+” tab to add new windows. Add new GUI API commands gui tab showSplitControl and gui tab hideSplitControl to control the display of the buttons to split the window. Add new GUI API commands gui settings addDialog and gui settings removeDialog to add and remove a custom tab to the Preferences dialog. Add new GUI API command gui cone disableUpdate to disable the update of highlights and attributes...

RTLvision® PRO simplifies the visualization of large RTL designs, including third party IP and reused blocks. Using Concept’s award winning visualization technology, the tool provides the unique and effective graphical rendering of RTL code structures, allowing engineers to quickly appreciate design functionality. Supporting SystemVerilog, VHDL and Verilog, RTLvision PRO comes complete with a range of debug views such as a powerful waveform display, an interactive cone of influence window, and other displays for a complete, 360° picture of the device. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair RTLvision PRO 2025.0 Win Tested Picture Altair RTLvision PRO 2025.0 is a major release, the following features were fixed and/or added: Show the logic value at the...

EEvision is an online visualization and debugging solution that easily renders schematics of circuits, wiring harnesses and component attributes specific to individual development and maintenance situations. Taking original CAD data or proprietary data as input, schematics are automatically rendered and explored on-the-fly, allowing complex systems to be easily and quickly understood. Google-style live search features allow for precise information to be extracted from huge data files and displayed in an easy-to-understand fashion. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair EEvision 2025.0 Tested Picture Unlike development CAD systems and paper maintenance manuals, incremental schematics reduce the clutter of unnecessary detail, while highlighting key data to significantly accelerate development and debug. The views can be modified...

The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs. Available other versions: 2024.1 ,10.7 Siemens Questa Advanced Simulator 2025.1 Linux Tested Picture The QuestaSim verification solution delivers on these requirements for complex SoC designs. QuestaSim achieves industry-leading performance and capacity through aggressive, global compile and simulation optimization algorithms for SystemVerilog, VHDL, and SystemC. Meanwhile, its Questa Visualizer debug environment provides high-performance, high-capacity debugging for dramatic regression throughput improvements when running large test suites. QuestaSim Benefits Industry-leading high performance multi-language simulator High-performance, high-capacity unified debug Reference simulator for LRM compatibility UVM, SystemVerilog, VHDL, SystemC, and mixed language...

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Available versions: 2025.04 , 2024.04 , … Aldec Riviera-PRO 2025.04 Win/Linux64 Tested Picture Riviera-PRO 2024.04 New Release Key Highlights The SystemVerilog type operator can be used on the list of the actual parameters of classes and design units parameterized with type. The type operator can be used in the type specification of typedef. The modules parameterized with type can be bound to instances with the use of the bind statement. Assigning the value null to SystemVerilog covergroup defined in a class outside of the class constructor is...