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The Physical Layer Test System (PLTS) is the industry standard for signal integrity measurements and data post processing of high-speed interconnects such as cables, backplanes, PCBs and connectors. Keysight Physical Layer Test System (PLTS) 2024U1 Tested Picture Many signal integrity laboratories around the world have benefited from the power of PLTS in the R&D prototype test phase. Today’s 1.6 Tbps internet infrastructure demands multiport channel analysis to mitigate crosstalk issues that can cause bit errors. The new PLTS 2024 has now migrated to a powerful 64-bit application that enables deeper memory for large data files and achieves 16- or 32-port Sparameter measurements.

Modelithics Qorvo GaN Library 24.5.4 for use with Keysight Technologies’ Advanced Design System (ADS) and Cadence AWR Design Environment®. This release is compatible with Keysight ADS 2022 – 2024 Update 2 and Cadence AWR Design Environment 16 and 17.3+. The Modelithics Qorvo GaN Library is backward compatible with previous Modelithics library releases. This latest version offers new models for Qorvo’s QPD1035 (40 W) and QPD1035L (40 W) discrete GaN-onSiC HEMTs. The QPD1035 and QPD1035L are 40 W devices with load-pull validation of 4, 5 and 6 GHz and a max frequency of 6 GHz. Both models are non-linear models and include temperature scaling. Also available with this release are two new embedding models for TGF2977-SM (5 W) and QPD1022 (10 W)...

PathWave RFIC Design (GoldenGate) 2024 includes new capabilities which includes new Fast Envelope algorithm, Krylov GPU acceleration, SystemVue VTB updated package, updated support for TMI, new circuit simulation models, improvements in Vrituoso Integration and usability improvements. Go beyond traditional RF simulation to design, analyze, and verify radio frequency integrated circuits (RFICs). Achieve confidence with steady-state and nonlinear solvers for design and verification. Wireless standard libraries accelerate the validation of complex RFICs. accurately model components on silicon chips optimize designs with sweeps and load-pull analysis simulate RF designs in the Cadence Virtuoso and Synopsys Custom Compiler environments increase performance using Monte Carlo and yield analysis assess EVM for the latest communication standards early in the design phase utilize the latest foundry...

Arteris IP created the new technologies in FlexNoC 4 AI based on its learning from some of the world’s leading AI and DNN SoC design teams. Arteris IP customers developing AI chips include autonomous driving pioneer Mobileye, who recently licensed Arteris IP FlexNoC and Ncore interconnect IP for its next-generation EyeQ systems, Movidius, Cambricon, Intellifusion, Enflame, Iluvatar CoreX, Canaan Creative, and four other companies that have not been publicly announced. New capabilities in FlexNoC 4 and the new AI Package include: Automated topology generation for mesh, ring and torus networks – FlexNoC 4 AI enables SoC architects to not only generate AI topologies automatically but also edit generated topologies to optimize each individual network router, if desired. Multicast – FlexNoC 4 AI intelligent multicast optimizes the usage of on-chip and...

Empire XPU build antenna arrays, multi-layered circuits, EMC/EMI, work on radar analysis, thermal analysis, biomedical applications and many more. DNV Sima 2024 v4.8 Tested Picture The new update 9.0.1 has been released. Additional start/stop commands for reconnectable server Time-to-finish display support for new remote server Improved file selector for postprocessing equations Improvement for QTEM impedance calculation for classic PGA Fix for exception in edit conformal dielectric Improved Boolean subtract operation Improved handling of unicode errors in path names Farfield cut preview in 3D Design window Improvements for reconnectable remote server Support of multiple jobs request on reconnectable server Improved long name support for dielectric properties QTEM support for hollow coaxial lines Memorizing mirror plane in repeated operation Import / Export:...

Synopsys RTL Architect product represents the industry’s first physically-aware RTL analysis, exploration, and optimization system with signoff technology integration. Synopsys RTL Architect uses a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. Built on a unified data model, Synopsys RTL Architect directly leverages Synopsys world-class implementation and golden signoff solutions, including Synopsys PrimePower RTL, to deliver results that are accurate early in the design cycle. Synopsys RTL Architect enables designers to significantly reduce RTL development time and to achieve “Simply Better RTL.” Key Benefits Increase Productivity Reduce project schedule with faster runtimes and fewer frontend – backend iterations Predict PPA Fast, implementation prediction engine ensures the...

Arm Fast Models are 100% functionally accurate, flexible programmer’s view models of Arm IP. They enable you to develop and test software such as drivers, firmware, OS, and applications without physical hardware. They deliver full control over the simulation, enabling profiling, software and hardware debug, and trace analysis. ARM Fast Models 2024 v11.26 Tested Picture Fast Models are available for all the Cortex-A, Cortex-R, and Cortex-M series CPUs from Arm, alongside many peripherals such as UART modules, memory management units, direct memory controllers, and more. These virtual models are available in two forms: preconfigured fixed systems (with pre-defined cores, memory, and peripherals) called Fixed Virtual Platforms (FVPs); or with a toolset to configure custom Fast Model systems more representative of...

PathWave Signal Generatio is a signal creation for a wide range of general purpose or standards-based signals.Comprehensive PC-based software for flexible signal creation. Cellular, wireless connectivity, aerospace/defense, broadcasting and general purpose applications. Supports a wide variety of signal generation hardware. PathWave Signal Generation Desktop 2024 Update 1.0 Tested Picture Create Performance-Optimized Reference Signals Create calibrated signals, validated by Keysight, that conform to industry standards to help enhance the characterization and verification of your devices with or without impairments. Validate Component, Transmitter and Receiver Testing Easily create and playback customized waveforms for component testing with virtually distortion-free test signals. Generate fully channel-coded signals including real-time mode to evaluate the throughput of your receiver. Impairments can be also added to evaluate receiver...

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Riviera-PRO 2024.04 New Release Key Highlights The SystemVerilog type operator can be used on the list of the actual parameters of classes and design units parameterized with type. The type operator can be used in the type specification of typedef. The modules parameterized with type can be bound to instances with the use of the bind statement. Assigning the value null to SystemVerilog covergroup defined in a class outside of the class constructor is now allowed. Introduces a new approach for handling compilation unit scopes (CUS) of...

Raphae FX is the gold standard, 2D and 3D resistance, capacitance and inductance extraction tool for optimizing on-chip parasitic for multi-level interconnect structures in small cells. As a reference field solver, Raphael FX provides the most accurate parasitic models in the industry. Trusted by major foundries, interconnect parasitics generated by Raphael FX are included as part of their design reference guides. Synopsys Raphael FX 2024.03 Linux64 Tested Picture Benefits Analyze complex on-chip interconnect structures and the influence of process variation Create a parasitic database for both foundries and designers to study the effect of design rule change Generate accurate capacitance rules for layout parameter extraction tools Interface with Sentaurus Structure Editor to create and analyze arbitrary and complex 3D shapes...