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EEvision is an online visualization and debugging solution that easily renders schematics of circuits, wiring harnesses and component attributes specific to individual development and maintenance situations. Taking original CAD data or proprietary data as input, schematics are automatically rendered and explored on-the-fly, allowing complex systems to be easily and quickly understood. Google-style live search features allow for precise information to be extracted from huge data files and displayed in an easy-to-understand fashion. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair EEvision 2025.0 Tested Picture Unlike development CAD systems and paper maintenance manuals, incremental schematics reduce the clutter of unnecessary detail, while highlighting key data to significantly accelerate development and debug. The views can be modified...

The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs. Available other versions: 2024.1 ,10.7 Siemens Questa Advanced Simulator 2025.1 Linux Tested Picture The QuestaSim verification solution delivers on these requirements for complex SoC designs. QuestaSim achieves industry-leading performance and capacity through aggressive, global compile and simulation optimization algorithms for SystemVerilog, VHDL, and SystemC. Meanwhile, its Questa Visualizer debug environment provides high-performance, high-capacity debugging for dramatic regression throughput improvements when running large test suites. QuestaSim Benefits Industry-leading high performance multi-language simulator High-performance, high-capacity unified debug Reference simulator for LRM compatibility UVM, SystemVerilog, VHDL, SystemC, and mixed language...

IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins. HDL Works IO Checker 5.2 Rev1 Win/Linux Tested Picture The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour. Once the project and its rules are...

HDL Companion is the HDL designer’s Swiss army knife. It will help you to get and keep a good overview of any HDL design, including third party IP, legacy code and other HDL sources. Complete design directories and design files are dragged into HDL Companion and a complete design overview is created in seconds, uncovering information regarding numerous aspects of the design. The GUI offers many ways to navigate through the design and explore the details you’re looking for. HDL Works HDL Companion 3.3 Rev3 Win/Linux Tested Picture The embedded fuzzy parsers accept any SystemVerilog, VHDL or mixed HDL design code; even if the code is incomplete or contains errors. Syntactically correct HDL can also be linted to find problems...

EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you’re creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language – VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project. HDL Works EASE 9.5 Rev7 Win/Linux Tested Picture Features & Benefits Graphical design environment with automated generation of hierarchical VHDL or Verilog code Standards compliant: – VHDL: IEEE-1076 87, 93 & 2008 – Verilog: IEEE-1364 95, 2001,...

ALINT-PRO is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design. Available versions:...

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Available versions: 2025.04 , 2024.04 , … Aldec Riviera-PRO 2025.04 Win/Linux64 Tested Picture Riviera-PRO 2024.04 New Release Key Highlights The SystemVerilog type operator can be used on the list of the actual parameters of classes and design units parameterized with type. The type operator can be used in the type specification of typedef. The modules parameterized with type can be bound to instances with the use of the bind statement. Assigning the value null to SystemVerilog covergroup defined in a class outside of the class constructor is...

Calibre Design Solutions is the industry leader for IC verification, delivering a complete IC verification and DFM optimization EDA platform that speeds designs from creation to manufacturing, addressing all sign-off requirements. Siemens Calibre 2024.2 Linux Tested Picture Calibre Design Solutions Portfolio Calibre Design Solutions delivers the most accurate, most trusted, and best-performing IC sign-off verification and DFM optimization in the EDA industry. Calibre Physical Verification The Calibre nmDRC Platform provides foundries, IDMs, and fabless companies with comprehensive, innovative verification technology for all nodes and processes. Calibre Circuit Verification The industry-leading Calibre circuit verification toolsuite includes layout vs. schematic (LVS) checking, reliability verification, and parasitic extraction. Calibre Reliability Verification Calibre reliability verification performs checks against electrical and physical design rules and...

Device Modeling MBP is a one-stop solution that provides both automation and flexibility for high-volume model generation. The software includes automated extraction packages for industry standard models as well as an open interface for modeling strategy customization. Turnkey solutions are also provided for the advanced statistical and mismatch model extraction, layout proximity effects (LPE) modeling, static random access memory (SRAM) cell modeling, HVMOS modeling, scalable Inductor modeling and corner library generation. Keysight Model Builder Program (MBP) 2025 Update 1.0 Tested Picture Device Modeling MBP is a complete modeling solution that integrates SPICE simulation, model parameter extraction and model library generation. The software supports the latest standard models including BSIM-BULK, BSIM-CMG and BSIM-IMG for logic, analog and RF designs. Besides compact...

Device Modeling MQA is an industry standard, automated SPICE model validation software. The software can check and analyze SPICE model libraries, compare different models, and generate QA reports in a complete and efficient way. The Device Modeling MQA software enables you to: Automate the QA process Easily identify model issues Standardize model validation flow Customize knowledge-based checking routines Freely compare between models/foundries/technologies One-click QA report generation