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S-Litho represents advanced lithography simulation for semiconductor device manufacturing process development and optimization. It covers a wide range of applications in proximity printing, optical, immersion, extreme ultraviolet (EUV), and electron beam (e-beam) lithography. Process-limiting effects within the imaging system of an exposure tool can be thoroughly analyzed, taking the impact of mask and substrate topography on photoresist patterning into account. Interfacing S-Litho with Synopsys TCAD tools allows a seamless modeling of complex integration techniques such as double-patterning. The link between S-Litho and Synopsys Proteus mask synthesis applications accelerates the generation and validation of optical proximity correction (OPC) models and improves process robustness. Synopsys S-Litho 2024.06 Win/Linux64 Tested Picture S-Litho provides a comprehensive set of features to predict the outcome of...

The Tweaker solution is the first and only complete ECO Platform with flexible flow control and integrated GUI, which handles all challenging capacity and complexity issues within ECO framework in a single machine. Everything is incremental As an ECO tool, Tweaker optimizes a design incrementally and locally, with minimal impact to the existing performance. In all of the ECO fixing operations, Tweaker only focuses on only critical portions of a design, known as the “ECO Domain”. For this reason, Tweaker can handle large designs in a very short turn-around time. Tweaker ECO covers all sign-off scenarios Timing/power optimization tools require MMMC (Multi-Mode, Multi-Corner) support as a basic ECO feature. Tweaker’s ECO-specific architecture takes the MMMC feature further by focusing only on the “ECO...

Sentaurus Process Explorer is a fast 3D process emulator used to identify and correct process integration issues during technology development. Synopsys Sentaurus Process Explorer 2024.03 Linux64 Tested Picture Sentaurus Process Explorer produces highly realistic 3D representations of process structures using GDSII mask data and a process recipe as input. Sentaurus Process Explorer is linked to the Synopsys TCAD simulators, such as Raphael FX, to enable the high accuracy RC extraction in Design Technology Co-Optimization (DTCO) applications.

The Physical Layer Test System (PLTS) is the industry standard for signal integrity measurements and data post processing of high-speed interconnects such as cables, backplanes, PCBs and connectors. Keysight Physical Layer Test System (PLTS) 2024U1 Tested Picture Many signal integrity laboratories around the world have benefited from the power of PLTS in the R&D prototype test phase. Today’s 1.6 Tbps internet infrastructure demands multiport channel analysis to mitigate crosstalk issues that can cause bit errors. The new PLTS 2024 has now migrated to a powerful 64-bit application that enables deeper memory for large data files and achieves 16- or 32-port Sparameter measurements.

Tanner, part of Siemens EDA’s Custom IC design solution, is packed with new features and improvements. Further product details L-Edit IC L-Edit is a complete hierarchical physical layout tool with cross-probe to schematic, layout and LVS & full integration with Calibre.Read more S-Edit Increases productivity for complex IC design, links to analog mixed simulation and schematic driven layout .Read more Tanner Calibre® One DRC/LVS/xRC The Tanner-Calibre One IC verification suite is an integral part of the Tanner analog/mixed-signal (AMS) physical design environment, creating an easy path to the proven capabilities of Calibre verification tools.Read more Tanner Designer Tanner Designer helps teams easily track analog verification throughout the entire design cycle.Read more Tanner Digital Implementer Integrated, flexible digital synthesis and place...

Modelithics Qorvo GaN Library 24.5.4 for use with Keysight Technologies’ Advanced Design System (ADS) and Cadence AWR Design Environment®. This release is compatible with Keysight ADS 2022 – 2024 Update 2 and Cadence AWR Design Environment 16 and 17.3+. The Modelithics Qorvo GaN Library is backward compatible with previous Modelithics library releases. This latest version offers new models for Qorvo’s QPD1035 (40 W) and QPD1035L (40 W) discrete GaN-onSiC HEMTs. The QPD1035 and QPD1035L are 40 W devices with load-pull validation of 4, 5 and 6 GHz and a max frequency of 6 GHz. Both models are non-linear models and include temperature scaling. Also available with this release are two new embedding models for TGF2977-SM (5 W) and QPD1022 (10 W)...

PathWave RFIC Design (GoldenGate) 2024 includes new capabilities which includes new Fast Envelope algorithm, Krylov GPU acceleration, SystemVue VTB updated package, updated support for TMI, new circuit simulation models, improvements in Vrituoso Integration and usability improvements. Go beyond traditional RF simulation to design, analyze, and verify radio frequency integrated circuits (RFICs). Achieve confidence with steady-state and nonlinear solvers for design and verification. Wireless standard libraries accelerate the validation of complex RFICs. accurately model components on silicon chips optimize designs with sweeps and load-pull analysis simulate RF designs in the Cadence Virtuoso and Synopsys Custom Compiler environments increase performance using Monte Carlo and yield analysis assess EVM for the latest communication standards early in the design phase utilize the latest foundry...

Arteris IP created the new technologies in FlexNoC 4 AI based on its learning from some of the world’s leading AI and DNN SoC design teams. Arteris IP customers developing AI chips include autonomous driving pioneer Mobileye, who recently licensed Arteris IP FlexNoC and Ncore interconnect IP for its next-generation EyeQ systems, Movidius, Cambricon, Intellifusion, Enflame, Iluvatar CoreX, Canaan Creative, and four other companies that have not been publicly announced. New capabilities in FlexNoC 4 and the new AI Package include: Automated topology generation for mesh, ring and torus networks – FlexNoC 4 AI enables SoC architects to not only generate AI topologies automatically but also edit generated topologies to optimize each individual network router, if desired. Multicast – FlexNoC 4 AI intelligent multicast optimizes the usage of on-chip and...

Empire XPU build antenna arrays, multi-layered circuits, EMC/EMI, work on radar analysis, thermal analysis, biomedical applications and many more. DNV Sima 2024 v4.8 Tested Picture The new update 9.0.1 has been released. Additional start/stop commands for reconnectable server Time-to-finish display support for new remote server Improved file selector for postprocessing equations Improvement for QTEM impedance calculation for classic PGA Fix for exception in edit conformal dielectric Improved Boolean subtract operation Improved handling of unicode errors in path names Farfield cut preview in 3D Design window Improvements for reconnectable remote server Support of multiple jobs request on reconnectable server Improved long name support for dielectric properties QTEM support for hollow coaxial lines Memorizing mirror plane in repeated operation Import / Export:...

Synopsys RTL Architect product represents the industry’s first physically-aware RTL analysis, exploration, and optimization system with signoff technology integration. Synopsys RTL Architect uses a fast, multi-dimensional implementation prediction engine that enables RTL designers to predict the power, performance, area, and congestion impact of their RTL changes. Built on a unified data model, Synopsys RTL Architect directly leverages Synopsys world-class implementation and golden signoff solutions, including Synopsys PrimePower RTL, to deliver results that are accurate early in the design cycle. Synopsys RTL Architect enables designers to significantly reduce RTL development time and to achieve “Simply Better RTL.” Key Benefits Increase Productivity Reduce project schedule with faster runtimes and fewer frontend – backend iterations Predict PPA Fast, implementation prediction engine ensures the...