2024-10-5 posts

Design Compiler® RTL synthesis solution enables users to meet today’s design challenges with concurrent optimization of timing, area, power and test. Design Compiler includes innovative topographical technology that enables a predictable flow resulting in faster time to results. Topographical technology provides timing and area prediction within 10% of the results seen post-layout enabling designers to reduce costly iterations between synthesis and physical implementation. Design Compiler also includes a scalable infrastructure that delivers 2X faster runtime on quad-core platforms. Design Compiler is the core of Synopsys’ comprehensive RTL synthesis solution, including Power Compiler™, DesignWare®, PrimeTime®, and DFTMAX™. Design Compiler NXT is also available and includes includes best-in-class quality-of-results, congestion prediction and alleviation capabilities, physical viewer, and floorplan exploration. Additionally Design Compiler NXT...

PrimeSim HSPICE simulator is seamlessly integrated with and empowered by other simulation engines in the continuum. PrimeSim HSPICE is the industry’s ‘gold standard’ for accurate circuit simulation and offers foundries-certified MOS device models with state-of-the-art simulation and analysis algorithms. With extensive usage in chip/package/board/backplane signal integrity simulation, cell and memory characterization, and analog mixed signal IC design, PrimeSim HSPICE is the industry’s most popular, trusted and comprehensive circuit simulator. To push the productivity frontier even further, PrimeSim HSPICE is fully integrated with the next generation design environment—PrimeWave, and ready to be used on the Cloud,where user could easily run, save and restore their simulations, anywhere and anytime. Synopsys PrimeSim HSPICE 2024.09 Win/Linux Tested Picture Foundries-Certified Models Device models are the...