Tag:Riviera-PRO

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Riviera-PRO 2024.04 New Release Key Highlights The SystemVerilog type operator can be used on the list of the actual parameters of classes and design units parameterized with type. The type operator can be used in the type specification of typedef. The modules parameterized with type can be bound to instances with the use of the bind statement. Assigning the value null to SystemVerilog covergroup defined in a class outside of the class constructor is now allowed. Introduces a new approach for handling compilation unit scopes (CUS) of...