Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Riviera-PRO 2024.04 New Release Key Highlights The SystemVerilog type operator can be used on the list of the actual parameters of classes and design units parameterized with type. The type operator can be used in the type specification of typedef. The modules parameterized with type can be bound to instances with the use of the bind statement. Assigning the value null to SystemVerilog covergroup defined in a class outside of the class constructor is now allowed. Introduces a new approach for handling compilation unit scopes (CUS) of...
Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Top Features and Benefits High Performance Simulation Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations The industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems Support for the latest Verification Libraries, including Universal Verification Methodology (UVM) Support for VHDL verification libraries, including OSVVM and UVVM. Advanced Debugging Integrated multi-language debug environment enables automating time-consuming design analysis tasks and fixing bugs...
ALINT-PRO is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design. Single Framework...
Active-HDL is a Windows based, integrated FPGA design creation and simulation solution for team-based environments. Active-HDL’s integrated design environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs. The design flow manager evokes 200+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flows and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from AMD, Intel, Lattice, Microchip, Quicklogic and more. Top Features and Benefits Project Management Unified Team-based Design Management maintains uniformity across local or remote teams Configurable FPGA/EDA Flow Manager interfaces with 200+ vendors tools allows teams to remain on one...
