EDA Page 3

Proteus ProGen models are empirical compact models reflecting the performance of a lithography process. Model parameters are determined by fitting experimental data. The Proteus Modeling Platform (PMP) provides a single environment for calibrating those parameters with a high degree of automation and tuning them for optimum performance in downstream applications. Synopsys ProGen 2023.12 Linux64 Tested Picture ProGen, Proteus’ highly customizable solution calibrates a single model that is utilized by both the space- and frequency-domain engines.

Synopsys Proteus™ full-chip mask synthesis smart manufacturing solutions enabling technologies down to 3nm and below. With the Synopsys Proteus family you can achieve exceptional precision, efficiency and speed in proximity correction, model building for correction, and analyzing proximity effects on corrected and uncorrected IC layout patterns, revolutionizing your chip fabrication process. The Synopsys Proteus full-chip mask synthesis family are the products of choice for leading edge IDMs and foundries and have been production proven for two decades with support for the latest EUV lithography processes. Synopsys Proteus 2023.12 Linux64 Tested Picture Key Benefits Largest Lithography Entitlement Industries first and most deployed inverse lithography solution with native curvilinear design and mask support. Fast Turn Around Time AI driven solutions with advanced...

Proteus WorkBench (PWB) is a powerful cockpit tool for the development and optimization of Proteus-based mask synthesis solutions. It is based on a powerful hierarchical GDSII/OASIS layout visualization and editing engine, providing a comprehensive environment for lithography simulation, compact model building, optical proximity correction (OPC) recipe tuning, litho rule checks, and mask synthesis flow development. Synopsys Proteus WorkBench 2023.12 Linux64 Tested Picture PWB offers an easy to use platform with access to a wide-ranging set of tools, enabling fast calibration of accurate models, supporting the optimization of highly efficient Proteus recipes for deployment in OPC and verification. As state-of-the-art lithography exposure tools are operated at their physical resolution limit, new mask and process technologies are being deployed to further shrink...

EasyPower 2024, with major new features including support for NFPA 70E 2024, Harmonics updates for IEEE 1547 and 2800, the ability to change names directly on the one-line, and a powerful new licensing service.  Other new features include improvements to data entry in the database browser, auto-calculated library information for more equipment, the ability to store and view arc flash calculations in the Database Browser, and support for Revit® 2024. EasyPower Advanced 2024 Tested Picture The following are the primary features included in the 2024 release. For additional features and release details, see EasyPower 2024 Release Details. EasyPower 2024 Update EasyPower 2024 (build 24.0.0.8071) fixes an issue that occurs when exporting a Revit project that includes demand factors. The issue causes the export...

Silvaco offers a full IC-CAD design flow including design capture, circuit simulation, layout design, physical verification, parasitic extraction and reduction, and post-layout analysis including statistical variation, and yield analysis. Silvaco SmartSpice Pro 2024 v5.9.2 Linux64 Tested Picture Schematic Editor Gateway is a highly productive environment with intuitive editing, capacity to support large and complex hierarchical or flat designs, ability to automatically generate symbols from existing legacy netlists and support for industry standard netlist and interface formats. It features tight integrations to Silvaco TCAD and analog custom design tools. Layout Editor Expert is a hierarchical IC layout editor featuring high capacity and flexible use across many silicon technologies in analog, mixed-signal, RF and digital circuits. As a key part of Silvaco’s custom IC...

TCAD software solutions are key to developing new semiconductor processes and devices, dramatically reducing costs and time to market.The package includes Victory TCAD,Legacy + Interconnect and Utmost IV. Silvaco DeckBuild 2024 v5.2.29 Linux64 Tested Picture Reduce Development Costs Reduce the time and manufacturing cycles spent to develop semiconductor technologies ITRS roadmaps indicates that TCAD simulation can reduce the costs during development cycles by ~30% Silvaco Tonyplot 2024 v3.10 Linux64 Tested Picture Visualize Internal Physical Processes Using simulation, you can see ‘inside” the device. Experimental measurements tell you what happens, but not why it happens. TCAD can tell you why. For example: Reverse voltage characterization on a power device tells you what happens at high reverse biases. The device experiences reverse breakdown at a specific voltage A TCAD...

EEvision tames electrical system complexity by dynamically isolating and visualizing critical regions. System-rendered displays show up-to-date schematics for system connectivity, wiring harnesses, and component attributes to help development teams, manufacturing teams, and service operations quickly understand real-time critical information in complex electrical systems. Digital twin model systems, generated using original ECAD data, proprietary data, or other standard formats, provide smart system visualization and automatic document creation. Users can extract precise information and display it in an easy-to-understand format with live searches that show electrical system functions and component influence, or drill down to specific component attributes linked to the digital twin model. Altair EEvision 2024.1 Tested Picture EEvision-2024.1 Fix the highlighting of UTF-8 characters in the GUI Search result window. The...

SpiceVision PRO takes SPICE netlists and models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, debug, and optimization at the transistor-level. Altair SpiceVision PRO 2024.1 Win Tested Picture SPICE circuits and models are the common currency of the EDA world. They are generated by many EDA tools and provide a description of the circuit at the lowest component abstraction level, the transistors, capacitors, resistors and even the interconnect that make up an IC or IP components. But for all but the most of trivial designs, SPICE files are very difficult to read and understand. SpiceVision PRO automatically generates visual circuit schematics, accelerates debug and helps to solve design problems in Digital Circuits, Mixed-Signal...

GateVision PRO is the third generation of graphical, gate-level netlist analyzers and viewers from Concept Engineering. Completely rewritten to run on modern 64bit platforms to handle the largest designs and SoCs, GateVision PRO provides a range of powerful debug and comprehension capabilities. These include intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation. Altair GateVision PRO 2024.0 Win Tested Picture Ultra-Fast Netlist Viewer – GateVision PRO is a high-performance and capacity gate-level debugger and viewer that can read and process the largest Verilog, EDIF and LEF/DEF netlists. GateVision PRO fits seamlessly into any design environment. Schematics are generated on the fly and the intuitive GUI lets the designer incrementally and easily...

RTLvision PRO simplifies the visualization of large RTL designs, including third party IP and reused blocks. Using Concept’s award winning visualization technology, the tool provides the unique and effective graphical rendering of RTL code structures, allowing engineers to quickly appreciate design functionality. Supporting SystemVerilog, VHDL and Verilog, RTLvision PRO comes complete with a range of debug views such as a powerful waveform display, an interactive cone of influence window, and other displays for a complete, 360° picture of the device. Altair RTLvision PRO 2024.0 Win Tested Picture  Mixed-HDL IP comprehension using Concept’s unique, leading RTL visualization approach, makes complex SoC functionality crystal clear  Advanced debug options, including waveform signal analysis, interactive logic cone and other specialized views, allow efficient bug eradication...