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EasyPower 2025, with major new features including support for NFPA 70E 2024, Harmonics updates for IEEE 1547 and 2800, the ability to change names directly on the one-line, and a powerful new licensing service.  Other new features include improvements to data entry in the database browser, auto-calculated library information for more equipment, the ability to store and view arc flash calculations in the Database Browser, and support for Revit® 2025. Available other versions: 24.00.00.8071 EasyPower Advanced 2025 Tested Picture EasyPower 2025 Update This topic describes new EasyPower features and enhancements, security improvements, and bug fixes that are included in the release. Features and Enhancements Store Short Circuit and Arc Flash Analysis Results in the Database Store Short Circuit and Arc Flash Results...

The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs. Available other versions: 2024.1 ,10.7 Siemens Questa Advanced Simulator 2025.1 Linux Tested Picture The QuestaSim verification solution delivers on these requirements for complex SoC designs. QuestaSim achieves industry-leading performance and capacity through aggressive, global compile and simulation optimization algorithms for SystemVerilog, VHDL, and SystemC. Meanwhile, its Questa Visualizer debug environment provides high-performance, high-capacity debugging for dramatic regression throughput improvements when running large test suites. QuestaSim Benefits Industry-leading high performance multi-language simulator High-performance, high-capacity unified debug Reference simulator for LRM compatibility UVM, SystemVerilog, VHDL, SystemC, and mixed language...

Design and Verification Tools (DVT) IDE is an integrated development environment for Verilog, SystemVerilog, Verilog AMS, VHDL, UPF, CPF, e Language, and PSS, helping design and verification engineers significantly improve their productivity. Unlike plain text editors providing regular expression-based capabilities, DVT IDE compiles the code and signals errors as you type, speeds up code writing using auto-complete and quick-fix proposals, and allows you to find anything you are looking for instantly. AMIQ DVT Eclipise IDE 2025 v25.1.8 Win/Linux Tested Picture DVT IDE enables engineers to overcome the limitations of plain text code editors and address today’s project complexity more efficiently. It enables faster and smarter code development and simplifies legacy code maintenance for novices and experts alike who work with...

IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins. HDL Works IO Checker 5.2 Rev1 Win/Linux Tested Picture The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour. Once the project and its rules are...

HDL Companion is the HDL designer’s Swiss army knife. It will help you to get and keep a good overview of any HDL design, including third party IP, legacy code and other HDL sources. Complete design directories and design files are dragged into HDL Companion and a complete design overview is created in seconds, uncovering information regarding numerous aspects of the design. The GUI offers many ways to navigate through the design and explore the details you’re looking for. HDL Works HDL Companion 3.3 Rev3 Win/Linux Tested Picture The embedded fuzzy parsers accept any SystemVerilog, VHDL or mixed HDL design code; even if the code is incomplete or contains errors. Syntactically correct HDL can also be linted to find problems...

EASE offers the best of both worlds with your choice of graphical or text based HDL entry. You don’t need to be a master of either Verilog or VHDL. When you’re creating a new design, just enter your design using your mix of graphics and text. EASE automatically generates optimized HDL code for you in the selected language – VHDL or Verilog. Industry standard version control environments deal with design and configuration management enabling multiple users to work simultaneously on one EASE project. HDL Works EASE 9.5 Rev7 Win/Linux Tested Picture Features & Benefits Graphical design environment with automated generation of hierarchical VHDL or Verilog code Standards compliant: – VHDL: IEEE-1076 87, 93 & 2008 – Verilog: IEEE-1364 95, 2001,...

PathWave Vector Signal Analysis (89600 VSA) is a comprehensive set of tools for demodulation and vector signal analysis. Discover signal analysis software tools to explore every facet of a signal and optimize your designs. Measure a broad range of signals including 5G, IoT, radar and more. Gain greater insight in frequency, time and modulation domains. Compatible with signal analyzers, network analyzers, oscilloscopes and many more test instruments. Keysight PathWave Vector Signal Analysis (89600 VSA) 2025 v29.00 Tested Picture Pinpoint Signal Problems Reach deeper into signals to find the root cause of problems in time, frequency, and modulation domains. Record and playback signals for troubleshooting. Isolate unexpected interactions with unlimited markers and trace-to-trace marker coupling. Measure All Your Signals Supports proprietary...

ALINT-PRO is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design. Available versions:...

Sim4Life V8.2.2 is the latest version of our online simulation platform for computational life science research, device design, and optimization, as well as safety and electromagnetic compliance evaluations. This new release introduces significant improvements to enhance your simulation experience and makes Sim4Life more user-friendly and efficient. ZMT Sim4Life 2025 v8.2.2 Tested Picture The highlights of Sim4Life.desktop V8.2.2: Electrostimulation Models: Four parameterized contact impedance models are now available which can be integrated with excitation pulses applied to neuron or thermal simulations. New Implant Routing Tools: Introducing the Routing Tool for simulating diverse implant paths and the Check Wire Path tool for visualizing tissue traversal by color-coding spline segments. Predefined Anatomical Postures: Easy access to predefined postures for common scenarios (standing, sitting, driving, etc.) with...

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards. Available versions: 2025.04 , 2024.04 , … Aldec Riviera-PRO 2025.04 Win/Linux64 Tested Picture Riviera-PRO 2024.04 New Release Key Highlights The SystemVerilog type operator can be used on the list of the actual parameters of classes and design units parameterized with type. The type operator can be used in the type specification of typedef. The modules parameterized with type can be bound to instances with the use of the bind statement. Assigning the value null to SystemVerilog covergroup defined in a class outside of the class constructor is...