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The Physical Layer Test System (PLTS) is the industry standard for signal integrity measurements and data post processing of high-speed interconnects such as cables, backplanes, PCBs and connectors. Available versions: 2025.x , 2024.x ,… Keysight Physical Layer Test System (PLTS) 2025U1 Tested Picture Many signal integrity laboratories around the world have benefited from the power of PLTS in the R&D prototype test phase. Today’s 1.6 Tbps internet infrastructure demands multiport channel analysis to mitigate crosstalk issues that can cause bit errors. The new PLTS 2024 has now migrated to a powerful 64-bit application that enables deeper memory for large data files and achieves 16- or 32-port Sparameter measurements.

StarVision® PRO represents the state-of-the-art in debug solutions for advanced electronic SoCs. The incorporation of Concept’s leading visualization and detection technology enables rapid cause-effect analysis for efficient functional analysis. This advanced and unique mixed-mode debug platform seamlessly combines SPICE and transistor analysis from our market leading SpiceVision PRO tool with digital RTL and gates from our advanced RTLvision PRO tool. It is fully customizable and incorporates many advanced features not available in other debug solutions, to handle the most complex of SoC platforms. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair StarVision PRO 2025.0 Win Tested Picture StarVision PRO 2025 is a major release, the following features were fixed and/or added: Show the logic value...

GateVision® PRO is the third generation of graphical, gate-level netlist analyzers and viewers from Concept Engineering. Completely rewritten to run on modern 64bit platforms to handle the largest designs and SoCs, GateVision PRO provides a range of powerful debug and comprehension capabilities. These include intuitive design navigation, netlist viewing, waveform viewing, logic cone extraction, interactive logic cone viewing for netlist debugging and design documentation. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair GateVision PRO 2025 Win Tested Picture GateVision PRO 2025 is a major release, the following features were fixed and/or added: Show the logic value at the mouse position in the tooltip of the Wave window. Speed-up displaying the members of large vectors in the Wave window. Add...

SpiceVision PRO takes SPICE netlists and models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, debug, and optimization at the transistor-level. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair SpiceVision PRO 2025.0 Win Tested Picture SpiceVision PRO 2025, the following features were fixed and/or added: Add new GUI API commands gui tab showPlusMenu and gui tab hidePlusMenu to control the display of the “+” tab to add new windows. Add new GUI API commands gui tab showSplitControl and gui tab hideSplitControl to control the display of the buttons to split the window. Add new GUI API commands gui settings addDialog and gui settings removeDialog to add and remove a custom tab to the Preferences dialog. Add new GUI API command gui cone disableUpdate to disable the update of highlights and attributes...

RTLvision® PRO simplifies the visualization of large RTL designs, including third party IP and reused blocks. Using Concept’s award winning visualization technology, the tool provides the unique and effective graphical rendering of RTL code structures, allowing engineers to quickly appreciate design functionality. Supporting SystemVerilog, VHDL and Verilog, RTLvision PRO comes complete with a range of debug views such as a powerful waveform display, an interactive cone of influence window, and other displays for a complete, 360° picture of the device. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair RTLvision PRO 2025.0 Win Tested Picture Altair RTLvision PRO 2025.0 is a major release, the following features were fixed and/or added: Show the logic value at the...

EEvision is an online visualization and debugging solution that easily renders schematics of circuits, wiring harnesses and component attributes specific to individual development and maintenance situations. Taking original CAD data or proprietary data as input, schematics are automatically rendered and explored on-the-fly, allowing complex systems to be easily and quickly understood. Google-style live search features allow for precise information to be extracted from huge data files and displayed in an easy-to-understand fashion. Available other versions: 2024.x , 2023.x , 7.1.x , 6.x , 5.x Altair EEvision 2025.0 Tested Picture Unlike development CAD systems and paper maintenance manuals, incremental schematics reduce the clutter of unnecessary detail, while highlighting key data to significantly accelerate development and debug. The views can be modified...

EasyPower 2025, with major new features including support for NFPA 70E 2024, Harmonics updates for IEEE 1547 and 2800, the ability to change names directly on the one-line, and a powerful new licensing service.  Other new features include improvements to data entry in the database browser, auto-calculated library information for more equipment, the ability to store and view arc flash calculations in the Database Browser, and support for Revit® 2025. Available other versions: 24.00.00.8071 EasyPower Advanced 2025 Tested Picture EasyPower 2025 Update This topic describes new EasyPower features and enhancements, security improvements, and bug fixes that are included in the release. Features and Enhancements Store Short Circuit and Arc Flash Analysis Results in the Database Store Short Circuit and Arc Flash Results...

The Questa advanced simulator is the core simulation and debug engine of the Questa verification solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs. Available other versions: 2024.1 ,10.7 Siemens Questa Advanced Simulator 2025.1 Linux Tested Picture The QuestaSim verification solution delivers on these requirements for complex SoC designs. QuestaSim achieves industry-leading performance and capacity through aggressive, global compile and simulation optimization algorithms for SystemVerilog, VHDL, and SystemC. Meanwhile, its Questa Visualizer debug environment provides high-performance, high-capacity debugging for dramatic regression throughput improvements when running large test suites. QuestaSim Benefits Industry-leading high performance multi-language simulator High-performance, high-capacity unified debug Reference simulator for LRM compatibility UVM, SystemVerilog, VHDL, SystemC, and mixed language...

IO Checker uses rules (based on regular expressions) to match the signal names in both the FPGA and PCB design environment. It allows the tool to validate groups of matches although individual signals can still differ. The rules can be generated automatically and be fine-tuned by the designer. The automated approach will often match 80% to 90% of all device pins. HDL Works IO Checker 5.2 Rev1 Win/Linux Tested Picture The flexibility of IO Checker allows it to be used in any design flow and does not require any design methodology. The rules generator in combination with the sorted problem view allows engineers to validate a 1000+ pins device in half an hour. Once the project and its rules are...