EDA
Electrical & Power Engineering softwares.
Synopsys 3DIC Compiler 2024.09 Linux Synopsys Avalon 2024.09 Linux Synopsys Certitude 2025.06/2024.09 Linux Synopsys Chamber Matching 2022.12 Synopsys CODE V 2025.03 Synopsys LightTools 2025.03 Synopsys LucidShape 2024.09 Synopsys LucidShape CAA V5 Based 2024.09 Synopsys coreTools 2025.06/2024.09 Linux64 Synopsys Custom Compiler 2024.09-SP1 Linux Synopsys Custom WaveView 2025.06 Synopsys DVE 2025.06/2024.09 Linux64 Synopsys Embedit 2025.06 Linux64 Synopsys ESP 2024.09 Linux64 Synopsys Euclide 2025.06 Win/Linux Synopsys FineSim 2025.06 Linux64 Synopsys Formality 2025.06/2024.09 Linux64 Synopsys Fusion Compiler 2025.06/2024.09 Linux64 Synopsys HSPICE 2025.06/2024.09 Win64/Linux64 Synopsys IC Compiler 2025.06/2024.09 Linux64 Synopsys IC Compiler II 2025.06/2024.09 Linux64 Synopsys IC Validator 2025.06/2024.09 Linux64 Synopsys IC Validator Workbench 2024.09 Linux64 Synopsys ICE Speed Adaptor 2023.09 Linux64 Synopsys Laker OA 2023.09 Linux64 Synopsys Library Compiler 2025.06/2023.12-SP3 Linux64 Synopsys LucidDrive 2024.03...

SpiceVision PRO tool with digital RTL and gates from our advanced RTLvision PRO tool. It is fully customizable and incorporates many advanced features not available in other debug solutions, to handle the most complex of SoC platforms. Available versions: 2026.x , 2025.x ,… Altair StarVision PRO 2026.0 Tested Picture Advanced, General-Purpose Debug IP-Based SoC Debug – Working with third party IP requires the comprehension of unfamiliar code. Concept’s visualization technology allows unfamiliar sections of the SoC to be easily understood, enabling fast IP integration and problem resolution. Due to the many different data formats supported by StarVision PRO engineers can explore, analyze and debug almost any SoC and IP building block within a single, easy-to-use debug cockpit. Path Extraction & Logic...

SpiceVision PRO takes SPICE netlists and models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, debug, and optimization at the transistor-level. Available versions: 2026.x , 2025.x ,… Altair SpiceVision PRO 2026.0 Tested Picture Advanced Debug and Analysis Interactive Cone Window – To accelerate debug, critical circuit portions can be graphically displayed in the Cone Window. Developers can concentrate on critical circuit fragments, with links to the original SPICE source code, while ignoring irrelevant design areas. This highly interactive view allows engineers to automatically build up critical paths through a design to rapidly find bug drivers. Complex bugs may be located and fixed quickly and easily. Circuit fragments displayed in the cone windows can easily...

RTLvision PRO simplifies the visualization of large RTL designs, including third party IP and reused blocks. Using Concept’s award winning visualization technology, the tool provides the unique and effective graphical rendering of RTL code structures, allowing engineers to quickly appreciate design functionality. Supporting SystemVerilog, VHDL and Verilog, RTLvision PRO comes complete with a range of debug views such as a powerful waveform display, an interactive cone of influence window, and other displays for a complete, 360° picture of the device. Available versions: 2026.x , 2025.x ,… Altair RTLVision PRO 2026.0 Tested Picture Design Comprehension Interactive RTL Code Navigation – RTLvision PRO can read complex RTL code, and display the underlying circuits on the fly, providing engineers with an immediate understanding of...

Z-planner Enterprise™ is field-solver based PCB stackup planning and materials selection software that’s optimized for both the design of PCB stackups and the management of stackup design as part of the PCB design flow. Available versions: 2025.x ,… Z-zero Z-planner Enterprise 2025.1 Tested Picture Z-planner Enterprise Includes: HyperLynx field solver Unlimited Impedance groups and layer count Advanced stackup wizard Stackup manager for design reuse Detailed manufacturing properties and notes Excel stackup export Z-solver cross-section analysis Glass awareness and Glass-Weave Skew mitigation Fab stackup imports Compare fab stackups to spec Stackup DFM and DFSI Import/export from SI software More: Z-zero Z-planner Enterprise 2025.1

EXata Network Modeling(Scalable EXata) allows the user to create a network digital twin, for real-time network simulation and emulation that replicates the behavior of a network. The emulator provides an exact, high quality, reproduction of external behavior so that the emulated system is indistinguishable from the real system. Network Emulation software provides a cost-effective method of evaluating new network technologies before actual systems or networks are built. Available versions: 2025.x , 2024.x ,… Keysight EXata Network Modeling 2025 v8.3.1 Tested Picture EXata Network Modeling uses a software virtual network (SVN) to digitally represent the entire network, the various protocol layers, antennas, and devices. The system can interoperate, at one or more protocol layers, with real radios and devices to provide...

custom IC solution is a full design flow of integrated, best-in-class circuit simulators and Calibre, the industry solution for physical verification. Available versions: 2025.x , 2024.x ,… Siemens Custom IC(TannerTools) 2025.4 Tested Picture Siemens Custom IC tools consist of integrated front-end and back-end tools, from schematic capture, circuit simulation, and waveform probing to physical layout and simulation. Modules included in Siemens Custom IC tools are: L-Edit—three versions, one each for IC, MEMS and photonics layout design, LVS, and DRC; for more details, see L-Edit IC, L-Edit MEMS, and L-Edit Photonics. S-Edit—tool and viewer for schematic capture; for more details, see S-Edit. T-Designer—tool for managing analog simulation results and creating custom reports. T-Spice—tool for circuit simulation; for more details, see T-Spice Simulation. WaveTool—waveform viewing and analysis;...

ALINT-PRO™ 2025.12, delivering a new set of design rules and guidance for mixed-language projects. The update helps engineering teams improve correctness, maintainability, and IP interoperability when combining VHDL and Verilog/SystemVerilog within a single project. Available versions: 2025.x , 2024.x ,… Aldec ALINT-PRO 2025.12 Tested Picture As mixed-language development becomes increasingly common for IP reuse, third-party integration, and long-life product maintenance, design teams face challenges caused by ambiguous mapping, inconsistent parameter passing, and configuration misuse. ALINT-PRO 2025.12 reduces these risks with a focused set of best-practice rules aimed at preventing integration issues before simulation, synthesis, and downstream verification. “Mixed-language design is a reality for most FPGA and ASIC teams, but small instantiation and mapping inconsistencies can create time-consuming debug cycles,” said Louie De...

Custom WaveView™ ADV provides a complete transistorlevel analysis and debugging environment for pre-processing and post-processing SPICE and FastSPICE simulations. Custom WaveView ADV is integrated with Synopsys’ HSPICE®, FineSim® and CustomSim™ to streamline the debugging and analysis process for SPICE and FastSPICE simulation and increase design productivity. The combination of Custom WaveView ADV with Synopsys circuit simulators provides design teams with a high-performance,productive simulation debug and analysis environment for complex SoC design. Synopsys Custom WaveView ADV 2024.09 Win/Linux64 Tested Picture Custom WaveView ADV is a netlist-based debugging environment for SPICE and FastSPICE simulators such as HSPICE, FineSim and CustomSim. Custom WaveView ADV is also tightly integrated with Custom WaveView, enabling waveform cross-probing. Together, these tools aid designers in rapidly performing customized...
Tessent Silicon Lifecycle Management solutions include advanced debug, safety & security features and in-life data analytics to meet the evolving challenges of today’s silicon lifecycle. Ensure the highest test quality, accelerate yield ramp and improve safety, security and reliability across the silicon lifecycle using best-in-class solutions for design-for-test (DFT), debug and in-life monitoring plus powerful data analytics. Tessent Advanced DFT Address the challenges of in-system test for today’s complex SoCs and chiplets with market-leading logic and memory test products that combine capabilities in a powerful test flow to ensure total chip coverage. Tessent Embedded Analytics Close productivity gaps using actionable insights from embedded analytics that shorten total development time, accelerate debug and reduce risk and cost to ensure timely market...