EDA

custom IC solution is a full design flow of integrated, best-in-class circuit simulators and Calibre, the industry solution for physical verification. Available versions: 2025.x , 2024.x ,… Siemens Custom IC(TannerTools) 2025.4 Tested Picture Siemens Custom IC tools consist of integrated front-end and back-end tools, from schematic capture, circuit simulation, and waveform probing to physical layout and simulation. Modules included in Siemens Custom IC tools for 2023.2 are: L-Edit—three versions, one each for IC, MEMS and photonics layout design, LVS, and DRC; for more details, see L-Edit IC, L-Edit MEMS, and L-Edit Photonics. S-Edit—tool and viewer for schematic capture; for more details, see S-Edit. T-Designer—tool for managing analog simulation results and creating custom reports. T-Spice—tool for circuit simulation; for more details, see T-Spice Simulation. WaveTool—waveform viewing...

ALINT-PRO™ 2025.12, delivering a new set of design rules and guidance for mixed-language projects. The update helps engineering teams improve correctness, maintainability, and IP interoperability when combining VHDL and Verilog/SystemVerilog within a single project. Available versions: 2025.x , 2024.x ,… Aldec ALINT-PRO 2025.12 Tested Picture As mixed-language development becomes increasingly common for IP reuse, third-party integration, and long-life product maintenance, design teams face challenges caused by ambiguous mapping, inconsistent parameter passing, and configuration misuse. ALINT-PRO 2025.12 reduces these risks with a focused set of best-practice rules aimed at preventing integration issues before simulation, synthesis, and downstream verification. “Mixed-language design is a reality for most FPGA and ASIC teams, but small instantiation and mapping inconsistencies can create time-consuming debug cycles,” said Louie De...

Custom WaveView™ ADV provides a complete transistorlevel analysis and debugging environment for pre-processing and post-processing SPICE and FastSPICE simulations. Custom WaveView ADV is integrated with Synopsys’ HSPICE®, FineSim® and CustomSim™ to streamline the debugging and analysis process for SPICE and FastSPICE simulation and increase design productivity. The combination of Custom WaveView ADV with Synopsys circuit simulators provides design teams with a high-performance,productive simulation debug and analysis environment for complex SoC design. Synopsys Custom WaveView ADV 2024.09 Win/Linux64 Tested Picture Custom WaveView ADV is a netlist-based debugging environment for SPICE and FastSPICE simulators such as HSPICE, FineSim and CustomSim. Custom WaveView ADV is also tightly integrated with Custom WaveView, enabling waveform cross-probing. Together, these tools aid designers in rapidly performing customized...

PrimeSim HSPICE is the industry’s ‘gold standard’ for accurate circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms. With extensive usage in chip/package/board/backplane signal integrity simulation, cell and memory characterization, and analog mixed signal IC design, PrimeSim HSPICE is the industry’s most popular, trusted and comprehensive circuit simulator. Available versions: 2025.x , 2024.x ,… Synopsys PrimeSim HSPICE 2025.6 Win64 Tested Picture PrimeSim™ SPICE is a high-performance SPICE circuit simulator for analog, RF, and mixed-signal applications. PrimeSim SPICE offers a unique multi-core/multi-machine scaling and heterogeneous compute acceleration on GPU/CPU delivering faster runtime with sign-off accuracy. PrimeSim SPICE supports high-frequency noise analysis, efficient S-Parameter handling while offering advanced analysis capabilities for periodic and non-periodic time-domain and frequency-domain...

Aprisa is a detail-route-centric physical design solution for the modern SoC. Whether your goal is to speed time to tapeout, reduce total cost of ownership, or achieve the lowest power usage, Aprisa is here with patented technologies and best-in-class support to ensure your success. Aprisa offers complete functionality for top-level hierarchical design and block-level implementation for complex digital IC designs. Its detail-route-centric architecture and hierarchical database enable fast design closure and optimal quality of results (QoR) at a competitive runtime. Siemens Aprisa 2023.1 Linux Tested Picture Reduced time-to-design closure A unified data model brings real route information and parasitics to any engine and step in the flow. Designers can confidently know their design’s achievable PPA at pre-route stage, greatly reducing...

Solido Design Environment is a comprehensive AI-powered design environment for all SPICE-level design and verification, and is a single unified solution for nominal and variation analysis. Used by thousands of designers to produce the most competitive products in hp computing, AI, IoT, automotive and mobile applications. Brute force-accurate signoff variation 1000X faster Orders of magnitude faster than brute-force simulation Full coverage verification across PVTs and Monte Carlo Brute-force Monte Carlo and SPICE accurate high-sigma verification Variation-aware design sensitivity, debugging and optimization Comprehensive design environment to boost engineering efficiency Significantly reduces documentation time/effort Identifies design weaknesses previously undetectable Easy to use and deploy Intuitive GUI for interactive design and analysis GUI or batch mode Works with all process technologies Integrated with...

Ansys Totem is the proven, trusted industry leader for power noise and reliability signoff for analog and mixed-signal designs built on cloud-native elastic compute infrastructure. Available versions: 2025.x ,2024.x ,2023.x ,… ANSYS Totem/Totem-SC 2025R2.2 Linux64 Tested Picture Ansys Totem revolutionizes transistor-level power integrity and reliability analysis, empowering users to conduct thorough assessments on analog mixed-signal IP and full-custom designs. It reshapes the conventional flow of analog mixed-signal power noise and reliability analysis by accommodating various design environments for modeling and characterization. Totem boasts a robust extraction and simulation engine, complemented by an intuitive graphical interface for in-depth root cause analysis and debugging of results. Power Integrity and Noise Verification at Transistor Level Totem-SC offer an ultra high-capacity version of Totem...

RedHawk-SC is the proven, trusted industry leader for power noise and reliability signoff for digital IP and SoCs down to 3nm and built on cloud-native elastic compute infrastructure Available versions: 2025.x ,2024.x ,2023.x ,… ANSYS Redhawk 2025R2.2 Linux64 Tested Picture RedHawk-SC is the premier solution for power noise and reliability signoff, renowned for its reliability in digital IP and SoCs scaling down to 3nm. It boasts a cloud-native elastic compute infrastructure, ensuring scalability and flexibility to meet the evolving demands of semiconductor design. As the trusted industry leader, RedHawk-SC provides comprehensive support for power integrity verification, enabling designers to achieve optimal performance and reliability in their designs while leveraging cutting-edge technology and cloud resources. IR-drop signoff Thermal-aware EM analysis Timing...