SMASH 7.6.0 mixed-signal simulator significantly speeds up OP/DC and transient analyses of analog and mixed designs in advanced nodes by a gain between x2 and x6. These major speed-up gains have been possible thanks to new methods and algorithms without losing simulation accuracy, as merge of identical SPICE instances, improve evaluation of MOS transistors, RC reduction methods and new Solver.
All these features allow SMASH to be as fast or even to overtake the major fastest golden spice simulators, while ensuring accuracy of a single solver SPICE simulator.
SMASH is now supporting SystemVerilog language for RTL synthesizable simulations, thanks to the integration of Verilator. Verilator is open source Verilog/SystemVerilog simulator. Verilator converts Verilog HDL modules to C++ models which are simulated by SMASH.
SLED 3.6 improves the user experience by allowing to:
- show/hide instance pin of instance elements in a schematic to simplify the schematic and improve its readability when a pin is optional
- set the color of instance elements in a schematic by TCL script to change the graphical representation of an instance depending on its parameter values
- define tags in parameter definition to bring order when a cell contains tens of parameter
- filter the parameter by tag in the property editor to highlight certain parameters according to their meaning/usage
