Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
Riviera-PRO 2024.04 New Release Key Highlights
- The SystemVerilog type operator can be used on the list of the actual parameters of classes and design units parameterized with type. The type operator can be used in the type specification of typedef. The modules parameterized with type can be bound to instances with the use of the bind statement.
- Assigning the value null to SystemVerilog covergroup defined in a class outside of the class constructor is now allowed.
- Introduces a new approach for handling compilation unit scopes (CUS) of files compiled in a single alog invocation.
- Hierarchical references from the SystemVerilog part of the design to objects declared in a VHDL instance are supported.
- The SystemVerilog DPI svGetTimeUnit() and svGetTimePrecision() functions from IEEE Std 1800™-2023 are supported.
- A preliminary support for the vpiStructNet and vpiUnionNet VPI C data types has been added. The types provide access to the SystemVerilog structures and unions of nets on the C side of the VPI interface, respectively.
- The osvvm and osvvm_common libraries have been updated to version 2024.03
- The uvvm_util and uvvm_vvc_framework libraries have been updated to version 2024.03.08
- The MATLAB interface offers the extended support of numeric types by allowing the use of the numeric_std and std_logic_arith packages of the IEEE library.
